Error (10818):vhdl
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Error (10818):vhdl
Error (10818):Can't infer register for "a0[0]" at shiftreg.vhd(96) because it does not hold its value outside the clock edge
PROCESS(clk_in,clk_5)
BEGIN
IF clk_5'EVENT AND clk_5='1' THEN
a16
Error (10818):Can't infer register for "a0[0]" at shiftreg.vhd(96) because it does not hold its value outside the clock edge
PROCESS(clk_in,clk_5)
BEGIN
IF clk_5'EVENT AND clk_5='1' THEN
a16
![Error (10818):vhdl](/uploads/image/z/8794145-65-5.jpg?t=Error+%2810818%29%3Avhdl)
一个进程process只能检测一个信号边沿,所以会有这样的.
你设计的原意大概是这样的吧:时钟上升沿的的时候采样数据,然后在clk_5的上升沿循环读入数据.
有如下两种处理方法
1.用一个process进行处理,不检测clk_5上升沿,直接检测高电平,但是在给clk_5高电平之前要能够保证a的数据已经是想要得到的数据.
PROCESS(clk_in,clk_5)
BEGIN
IF clk_in'EVENT AND clk_in='1' THEN
a0
你设计的原意大概是这样的吧:时钟上升沿的的时候采样数据,然后在clk_5的上升沿循环读入数据.
有如下两种处理方法
1.用一个process进行处理,不检测clk_5上升沿,直接检测高电平,但是在给clk_5高电平之前要能够保证a的数据已经是想要得到的数据.
PROCESS(clk_in,clk_5)
BEGIN
IF clk_in'EVENT AND clk_in='1' THEN
a0
Error (10818):vhdl
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